programming report and need the explanation and answer to help me learn.
all the information is in the file.
Requirements:
Coursework (ENG2025 Digital Electronics 2022-23) 1) Design using VHDL with EDA Playground, a 4 x 4-bit parallel multiplier using the correct number of adder blocks – full-adders (FAs) and half-adders (HA). This must include the AND gates to generate the product terms and use the carry-save method with a ripple-carry adder in the final row (CLA adder is not required in the last row). a. You would need to use the RTL level design for the basic gates, i.e., AND, OR, XOR, etc. gates. Then, FAs and HAs need to be implemented using the structural (or logic gate) level design. Finally, the final parallel adder requires the structural (or logic gate) level design for connecting the AND gates, FAs and HAs. b. Per each of the basic gates, consider the delay based on the architecture, i.e., AND gates delay; c. Show simulation results by designing a dedicated testbench (i.e., testbench.vhd) and using Open EPWave with different input values in the range of 0-15. d. You should explain in a short report the design process and choices (up to 2 pages max). 2) Design in VHDL, using EDA Playground, a 4-bit serial multiplier. You can choose either an 8-bit Adder, as shown in Fig. 1, in which, by relying on a CLK signal, the following operations are repeatedly executed to obtain the final result: 1. Load R and D; Clear P to 0 (only the first time); 2. Add the partial product (r0 AND D) to P; 3. Shift R right 1 bit; Shift D left 1 bit; 4. Repeat from step 2 a total of 4 times. Fig. 1 4×4-bit multiplier using an 8-bit Adder Or, you can choose a 4-bit Adder, as shown in Fig. 2.
Fig. 2 4×4-bit multiplier using a 4-bit Adder (smaller version) a. You would need to use a structural (or logic gate) level and RTL level design, processes, and event-based logic for the memory elements. b. Consider the delay based on the adder architecture, i.e. 4-bit adder; c. Show simulation results by designing a dedicated testbench (i.e., testbench.vhd) and using Open EPWave with different input values in the range of 0-15. d. You should explain in a short report the design process and choices (up to 2 pages max). Important: these designs use registers (such as shift registers), for example, the Multiplicand D, Multiplier R, and Result Register P. 3) If you have implemented both designs, provide a comparison in terms of delay between parallel vs serial implementation and also in comparison with theory (i.e., equations). Submission Submit the *.vhd source files and testbench.vhd file plus the report(s) on CANVAS in a single zip file. Deadline the 24th of April. Marking scheme This coursework contributes 20% to the total module mark. To get the mark, you are expected to complete at least one of the two questions, 1) or 2), and this will give a mark of up to 12%. If you answer both questions, 1) and 2), you can get a mark of up to 18%. If you then address also question 3) you can get mark up to 20%.